1. Field of the Invention
The present invention relates to semiconductor memory devices and, more specifically to a semiconductor memory device performing a CBR (CAS before RAS) refresh operation.
2. Description of the Background Art
Stored information is retained in a DRAM (Dynamic Random Access Memory) by accumulating electric charges in a capacitor provided in a memory cell. Accordingly, a refresh operation must periodically be performed to prevent disruption of the stored information by a leakage current. In the refresh operation, word lines provided correspondingly to rows of the memory cells are sequentially selected, and accumulated electric charges are read for all memory cells on the selected word lines and rewritten after amplification. Thus, a voltage at a storage node in the memory cell is reset at an initial value even if it has been reduced by the leakage current. By continuing to sequentially select all of the word lines, the stored information in all memory cells are reproduced, so that the stored information for the entire chip can be retained.
Here, assume that a maximum value of a refresh interval assuring prevention of data disruption for every memory cell is trefmx and the number of word lines is N. Then, a relationship of tcrf.ltoreq.trefmx/N must be held to enable a refresh operation with a given refresh cycle tcrf corresponding to an interval between word lines in order to prevent disruption of stored information by a leakage current. Accordingly, if the number of word lines increases due to an increase in a storage capacity of memories, the refresh cycle must correspondingly be reduced. Thus, in a DRAM with a large storage capacity, a refresh cycle is ensured by increasing the number of word lines simultaneously selected during a refresh operation as compared with that during a normal reading/writing operation in order to increase the number of rows subjected to a single refresh operation.
There are two types of refresh operations: a refresh operation performed during a random access operation such as a reading/writing operation; and a refresh operation performed only for retaining stored information in a chip as performed during a battery backup period. Especially in the former refresh operation, a CBR (CAS before RAS) refresh has been widely used in terms of saving the number of terminals. In the CBR refresh, the start of the refresh operation is instructed by reversing the order of activating a row address strobe signal /RAS and a column address strobe signal /CAS, which are inherently control signals, with respect to the order during a normal reading/writing operation without providing a control signal dedicated to the refresh operation.
FIG. 14 is a schematic diagram showing a memory array 500 of a DRAM structured to select a greater number of word lines during the refresh operation than during a normal operation.
While not shown in the drawing, memory array 500 has a plurality of memory cells arranged in a matrix. Here, memory array 500 is of a 64-Mbit size addressed by address bits A0 to A12 of an address signal of 13 bits. Memory array 500 is divided into two regions 500a and 500b of the same size in a row direction. In each of regions 500a and 500b, word lines are provided correspondingly to rows of the memory cells.
For row selection, the last bit A12 of the address signal is used for selecting one of regions 500a and 500b of the memory array. In each of regions 500a and 500b, one memory cell row is selected and a corresponding word line is activated in accordance with a combination of the remaining address bits A0 to A11 of 12 bits. Thus, the word lines corresponding to the same combination of signal levels of address bits A0 to A11 are provided in both of regions 500a and 500b.
FIG. 14 representatively shows word lines WLa and WLb correspondingly designated by address bits A0 to A11 in regions 500a and 500b. Word drivers WDa and WDb are respectively provided for word lines WLa and WLb.
Word driver WDa receives a block selection signal RAD12 set correspondingly to address bit A12, a word line activation signal RXT, and an address decode signal ADC activated in accordance with a combination of address bits A0 to A11 for driving word line WLa into a selection state when all of these signals are activated. For each of the other word lines provided in region 500a, a word driver is arranged which activates the corresponding word line in accordance with signals as in the case of word driver WDa.
On the other hand, word line driver WDb receives a block selection signal ZRAD12 which is complementary to block selection signal RAD12 in accordance with address bit A12 as well as word line activation signal RXT and address decode signal ADC also applied to word driver WDa for operation.
During normal reading and writing operations, one of block selection signals RAD12 and ZRAD12 is activated (H level) in response to a signal level of address bit A12, and a word line corresponding to address bits A0 to A11 is activated in one of regions 500a and 500b. On the other hand, during a refresh operation, both of block selection signals ZRAD12 and RAD 12 are activated (H level) regardless of the signal level of address bit A12. Thus, in this case, corresponding word lines are activated in regions 500a and 500b in accordance with a combination of address bits A0 to A11. Accordingly, in memory array 500, twice as many word lines are simultaneously activated during the refresh operation as compared with the case of the normal operation. Such a structure ensures a refresh cycle for the memory cell array with a large storage capacity.
FIG. 15 is a timing chart shown in conjunction with a row related operation during a normal operation of memory array 500.
Referring to FIG. 15, /RAS is a row address strobe signal designating activation of a row related operation. /CAS is a column address strobe signal designating activation of a column related operation. A12 represents a signal level of address bit A12, and control signals RASF and CAS are respectively inverted signals of row address strobe signal /RAS and column address strobe signal /CAS, obtained as outputs from a control signal.
A signal ZRASE is an inverted signal of control signal RASF, and a control signal RADE is a row address decode enable signal activated when a prescribed period of time is elapsed after activation of row address strobe signal /RAS in response to the start of the row related operation.
One of block selection signals ZRAD12 and RAD12 is activated in accordance with the signal level of address bit A12 during the normal operation. Control signals RXT and S0N are respectively a word line activation signal and a sense amplifier activation signal. Activation timings for signals RXT and S0N are controlled such that the word line and the sense amplifier are suitably timed to be activated in response to the start of the row related operation.
A refresh control signal ZCBR is inactivated (H level) during the normal operation and activated (L level) for designating a refresh operation for CBR refresh. Thus, when refresh control signal ZCBR is activated, both of block selection signals ZRAD12 and RAD12 are activated (H level). When refresh control signal ZCBR is inactivated (H level), one of block selection signals ZRAD12 and RAD12 is activated (H level) in accordance with the signal level of address bit A12.
Thus, when row address strobe signal /RAS is activated and the row related operation starts at a time t0, responsively, control signals RASF and ZRASE are sequentially activated (level) and row address decode enable signal RADE, word line activation signal RXT and sense amplifier activation signal S0N are activated. Block selection signal ZRAD12 corresponding to the signal level (L level) of address A12 is activated (H level) in response to activation of row address decode enable signal RADE, and RAD 12 is maintained in an inactivation state (L level). Thus, only the word lines in region 500b are subjected to activation.
Further, the column related operation starts in response to activation of column address strobe signal /CAS at a time t1, and a data reading/writing operation is performed on memory cells in region 500b selected by the address signal.
FIG. 16 is a circuit diagram showing a structure of a conventional refresh control circuit 510 generating a refresh control signal ZCBR.
Referring to FIG. 16, refresh control circuit 510 includes an SR flip flop 512 receiving two inputs of control signals CAS and RASF, and an SR flip flop 514 receiving two inputs of control signal RASF and control signal ZRF which is an output from SR flip flop 512. SR flip flop 514 outputs a refresh control signal ZCBR.
FIG. 17A shows states of control signal ZRF in relation to a combination of control signals RASF and CAS, corresponding to a truth table of SR flip flop 512. Similarly, FIG. 17B shows states of refresh control signal ZCBR in relation to a combination of control signals ZRF and RASF, corresponding to a truth table of SR flip flop 514.
FIG. 18 is a timing chart shown in conjunction with a row related operation for CBR refresh in memory array 500.
Referring to FIG. 18, during a CBR refresh operation, column address strobe signal /CAS is activated prior to activation of row address strobe signal /RAS (time t0). This corresponds to the state in which control signal CAS is risen to the H level when control signal RASF is at the L level, so that control signal ZRF is correspondingly set at the L level.
Thereafter, when control signal RASF changes from the L to H level in response to activation of row address strobe signal /RAS (time t1), refresh control signal ZCBR is activated (L level) while control signal ZRF is maintained at the L level.
In response to activation of refresh control signal ZCBR, block selection signal ZRAD12 is activated (H level) in addition to block selection signal ZRAD12 activated in response to the signal level of address bit A12. In this state, control signals RXD and S0N are sequentially activated, so that corresponding word lines and sense amplifiers are also sequentially activated. Thus, in each of two regions 500a and 500b shown in FIG. 14, a refresh operation can be performed on the corresponding word lines.
The CBR refresh operation, once started, completes when control signal ZRF is brought back into the inactivation state (H level) in response to inactivation of row address strobe signal /CAS after control signal ZRF is inactivated (H level) in response to inactivation of column address strobe signal /CAS.
Referring to FIG. 17A and 17B, during the normal operation when row address strobe signal /RAS is activated prior to column address strobe signal /CAS, even if control signal RASF is activated (H level), control signal ZRF and a refresh control signal ZCBR are maintained in the inactivation state (H level), so that the normal reading/writing operation is performed.
In the structure of refresh control circuit 510 shown in FIG. 16, 5 however, if noise is superimposed on row address strobe signal /RAS when both of row address strobe signal /RAS and column address strobe signal /CAS are activated (L level) during the normal operation, erroneous activation of the refresh control signal may be caused, resulting in disruption of data in the memory cell. This will now be described in detail.
Returning to FIG. 15, assume that noise is superimposed on row address strobe signal /RAS at a time t2 and the row address strobe signal /RAS is temporarily brought into the inactive state (H level) and then returns back to the active state (L level). The levels of control signals RASF and /ZRASE change in response to the noise.
In the normal operation, both of control signal ZRF and refresh control signal ZCBR are at the H level at t2 at which the noise is caused. Thus, if the noise is superimposed on row address strobe signal /RAS thereby bringing and control signal RASF to the L level, the level of control signal ZRF responsively changes from H to L level.
Accordingly, if row address strobe signal /RAS returns back to the active state (L level), control signal RASF also returns back to the H level from the L level. Responsively, refresh control signal ZCBR is activated (L level). Thus, block selection signal RAD12 is newly activated in addition to block selection signal ZRAD12 which has been activated in response to the signal level of address bit A12. Responsively, the word line in region 500a, which is not essentially subjected to activation, is activated.
In region 500a which is not essentially subjected to activation, if the word line is activated when the sense amplifier is not activated, the sense amplifier may be activated at an incorrect timing before electric charges corresponding to stored information and accumulated in the memory cells connected to the word line are sufficiently transmitted to the bit line, thereby disrupting data in the memory cell. On the other hand, if the word line is activated in the state in which the sense amplifier for region 500a is activated, the data in the memory cell connected to the word line may be disrupted as electric charges from the memory cells are not amplified by the sense amplifier.
FIGS. 19A and 19B are timing charts shown in conjunction with activation timings of the word line and sense amplifier as well as data reading.
FIGS. 19A and 19B show an operation of reading retained data to the bit line by activation of the bit line and sense amplifier for the memory cell in which data at the H level is retained. In the drawing, VWL represents a voltage level of the word line, control signal S0N represents an activation signal for the sense amplifier, and VBL represents a voltage level of the bit line.
FIG. 19A shows a correct activation timing at which the word line is activated prior to activation of the sense amplifier. Referring to FIG. 19A, bit line voltage VBL is set at a precharge potential Vpc before a time ta at which the word line is activated. Upon activation of the word line at ta, bit line voltage VBL is changed to reflect the H level of data retained in the memory cell.
The sense amplifier operates to amplify a potential difference between a complementary pair of bit lines in response to activation of sense amplifier activation signal S0N at a time tb, so that bit line voltage VBL is amplified to attain to the H level. Because of an appropriate time lag between ta and tb, even if the level of the bit line voltage gradually changes toward the direction opposite to the voltage level of the data retained in the memory cell immediately after the word line is driven, the sense amplifier is activated after the voltage level corresponding to the retained data appears as a bit line voltage. Thus, the voltage level of the data retained in the memory cell can correctly be amplified by the sense amplifier.
On the other hand, referring to FIG. 19B, bit line voltage VBL is changed to attain to the H or L level after a time tc at which the amplifier has already been activated. In this state, if the word line is selected at a time td so that electric charges move from the memory cell in response to the increase in word line voltage VWL, data of the memory cell is disadvantageously disrupted and lost due to a large driving current of the sense amplifier.
More specifically, when the CBR refresh operation is controlled by conventional refresh control circuit 510 shown in FIG. 16 and both of row address strobe signal /RAS and column address strobe signal /CAS are in the active state (L level) during a normal operation, if noise is caused to row address strobe signal /RAS, a refresh control signal may erroneously be activated, thereby disadvantageously causing disruption of data in the memory cell.